The present invention relates to a method of forming a trench for high voltage isolation in a semiconductor substrate.
Methods of forming a lithographic opening in a layer of a material in a semiconductor process are well known in the art. A lithographic opening is the smallest feature size in a semiconductor process that the particular process can produce. Thus, for example, in a 0.13 micron process, the smallest opening or feature size that the process can create would be an opening of 0.13 micron in size, which would be the lithographic feature for that process. A sublithographic opening would be an opening having dimensions that are smaller than the smallest feature size available for that lithographic process. Thus, any opening having a dimension less than 0.13 micron in a 0.13 micron process would be a sublithographic opening in a 0.13 micron process.
It is desirable in a lithographic process to form sublithographic openings in certain parts of the semiconductor structure to create a smaller feature size in order to handle problems such as misalignment or the like. In the prior art, it is known to create a sacrificial layer of a first material. A lithographic opening is created in the first layer of sacrificial material forming a lithographic opening therein. A second layer of a second material, different from the first material, is conformally deposited on the first layer. The second layer of the second material is then anisotropically etched until the first layer is reached. This creates spacers made of the second material in the opening in the first layer. The spacers in the opening of the first layer decreases the size of the opening thereby creating a sublithographic opening. The first layer of the first material along with the spacers of the second material is then used as a masking layer to create sublithographic openings in the layers upon which the first layer is deposited. See for example, U.S. Pat. No. 6,362,117. Such a process, however, requires the use of two layers of different materials to form a sacrificial masking layer. See also U.S. Pat. Nos. 6,365,451; 6,413,802; 6,429,125 and 6,423,475 on creation of sublithographic structures in a semiconductor structure.
Methods for forming trenches for isolation are also well known in the art. However, as the scale of integration increases, i.e., the size of the lithographic opening decreases, voltages used in applications involving high voltages such as non-volatile memory cell increases. Thus, the trenches that are needed to isolate higher voltage elements of the integrated circuits used in such applications need to be wider and deeper. Wider and deeper trenches which are used to support higher breakdown and higher isolation voltages than the prior art create problems in that as the trenches are filled with insulating materials which are much thicker than normal, the contour of the surface of the semiconductor becomes more ragged and thereby rendering more difficult to planarize the surface using conventional planarization techniques such as CMP polishing techniques. Since thicker insulating films required for deeper trench isolations is accompanied by larger variations of thickness compared to normal thickness, this makes the planarization process even more difficult to achieve. Therefore, it is desirable to form trenches for high voltage isolation which have less contour deviations on the surface than the prior art in order that subsequent planarization steps may be more effective.
The present invention relates to a method of creating a trench for high voltage isolation in a semiconductor substrate that has a first surface. A first trench is formed in the substrate. The first trench has sidewalls and a bottom surface with the first trench having a first width and a first depth. Spacers are formed along the sidewalls of the first trench with the spacers partially covering the bottom surface. A barrier layer is formed on portions of the bottom surface not covered by the spacers. The spacers are removed thereby exposing portions of the bottom surface not covered by the barrier layer. The bottom surface is etched in portions that are not covered by the barrier layer to form a second trench having sidewalls and a bottom surface. The second trench has a second depth. An insulating layer is conformally deposited on the first surface including filling the first and second trenches.